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NEXTEST MAGNUM I EV Automated Test Equipment for Sale


SDI fabsurplus.com is pleased to announce the availability of the following listed used NEXTEST MAGNUM I EV Automated Test Equipment.
Please click on the "Send More Details" button at the end of the MAGNUM I EV description, if you'd like to get more details, photos and specifications of this Automated Test Equipment, and your request for this equipment will be forwarded to our SDI sales representatives automatically.
This NEXTEST MAGNUM I EV Automated Test Equipment is available for immediate sale.
Crating, refurbishment and delivery for this equipment can be quoted on request.


NEXTEST MAGNUM I EV Equipment Details

SDI ID: 99381
Manufacturer: NEXTEST
Model: MAGNUM I EV
Description: Automated Test Equipment
Version: TEST
Vintage: Inquire
Quantity: 1
Sales Condition: as is where is
Lead Time: immediately
Sales Price: Inquire
Comments:

-In working condition

-See attached photo for details.

Diagnostics report:-

HSB1 SERIAL# xxxx
Loading TCal data from file: Y:\nextest\caldata\tcal_data_xxxxxx.bin
Loading VCAL Data on t_hsb1, t_pe32_1
Loading VCAL Data on t_hsb1, t_pe32_2
Loading VCAL Data on t_hsb1, t_pe32_3
Loading VCAL Data on t_hsb1, t_pe32_4
Loading VCAL Data on t_hsb1, t_dps_pmu_1
Loading VCAL Data on t_hsb1, t_dps_pmu_2
Loading VCAL Data on t_hsb1, t_dps_pmu_3
Loading VCAL Data on t_hsb1, t_dps_pmu_4
active dut = 0
The test program is loaded

TestStarted(1)...

Started: 04/29/20 09:43:30

- Site controller details -
Intel(R) Pentium(R) III CPU family      1266MHz, 509MB total physical memory.
Microsoft Windows XP
CSDVersion


- Revision Codes for Boards -

                                           Site 1 ( Chassis 1, Slot 1 )
  Board         Serial   PWB     PWB  PWA     PWA      LVM       DBM      ECR1      ECR2      X     Y     D
  Name          Number   Number  Rev  Number  Rev    SDR/DDR     MBits    MBits     MBits    bits  bits  bits
  -----------------------------------------------------------------------------------------------------------
  HSBX          xxxxxx   503539  2    507487  9      2/4     (2) 72  (2)  72  (2)   72  (2)  18*   16*   36*
  PEX_1         xxxxxxx  507466  1    507467  3
  PEX_2         xxxxxx   507466  1    507467  3
  PEX_3         xxxxxxx  507466  1    507467  3
  PEX_4         xxxxxx   507466  1    507467  3
  DP_1          xxxxxxx  504582  6    504583  15
  DP_2          xxxxxx   504582  5    504583  15
  DP_3          xxxxxx   504582  5    504583  15
  DP_4          xxxxxx   504582  4    504583  15
  IPC           xxxxxx   505306  5    505305  24    Firmware Revision : 3.8.4

* NOTE: The ECR X, Y, D bits represent the maximum allowable configuration.


- Revision Codes for Memory Modules -
  Module               Base    PWA      PWA     LVM     DBM     ECR
  Name                 Number  Number   Rev     MVec    MBits   MBits
  -------------------------------------------------------------------
  DBM-DIMM1            505479  505939   1               36
  DBM-DIMM2            505479  505939   1               36
  ECR1-DIMM1           505479  505933   1                       36
  ECR1-DIMM2           505479  505933   1                       36
  ECR2-DIMM1           505479  505933   1                       36
  ECR2-DIMM2           505479  505933   1                       36
  LVM1-DIMM1           505479  505946   1       2
  LVM2-DIMM1           505479  505946   1       2


- Revision Codes for FPGAs -
  FPGA         SW      HW
  Name         Rev     Rev
  -------------------------
  CPUI Fpga    0x1     0x9  
  TG1 Fpga     0x1     0x18 
  TG2 Fpga     0x1     0x18 
  TG3 Fpga     0x1     0x18 
  TG4 Fpga     0x1     0x18 
  TG5 Fpga     0x1     0x18 
  TG6 Fpga     0x1     0x18 
  TG7 Fpga     0x1     0x18 
  TG8 Fpga     0x1     0x18 
  APG1 Fpga    0x1     0xf1 
  APG2 Fpga    0x1     0xb0 
  DBM1 Fpga    0x1     0xbf 
  PSLE1 Fpga   0x1     0x88 
  PSS1 Fpga    0x1     0x90 
  PSLE2 Fpga   0x1     0x88 
  PSS2 Fpga    0x1     0x90 
  PSLE3 Fpga   0x1     0x88 
  PSS3 Fpga    0x1     0x90 
  PSLE4 Fpga   0x1     0x88 
  PSS4 Fpga    0x1     0x90 
  LVM1 Fpga    0x1     0x4c 
  LVM2 Fpga    0x1     0x4b 
  ECR1 Fpga    0x1     0xc3 
  ECR2 Fpga    0x1     0xc3 
 
Nextest software release:  C:\nextest\h2.3.17\Bin\Ui.exe
Running on MAGNUM_X20 system# xxxxxx
Testing APG read,write registers via cpu [apg_rw_regs_tb]
  Testing Address registers and LBDATA
  Testing MAR and INTA
  Testing JAM, DMAIN, DBASE, YINDEX
  Testing Unique values
Testing APG counter RAM - short march [apg_counter_ram_short_march_tb]
Testing APG reload RAM - short march [apg_reload_ram_short_march_tb]
Testing APG XDTOPO RAM - short march [apg_xdtopo_ram_short_march_tb]
Testing APG YDTOPO RAM - short march [apg_ydtopo_ram_short_march_tb]
Testing APG uRAM - short march [apg_uram_ram_short_march_tb]
Testing APG Cycle Length RAM - short march [apg_cycle_ram_short_march_tb]
Testing APG DAC RAM - short march [apg_dac_ram_short_march_tb]
Testing APG XTOPO RAM - short march [apg_xtopo_ram_short_march_tb]
Testing APG YTOPO RAM - short march [apg_ytopo_ram_short_march_tb]
Testing APG User RAM - short march [apg_user_ram_short_march_tb]
Testing APG vRAM - short march [apg_vram_ram_short_march_tb]
    Testing VMC1 DIMM1 - Bit Independence Test
    Testing VMC1 DIMM1 - Address Independence Test
    Testing VMC2 DIMM1 - Bit Independence Test
    Testing VMC2 DIMM1 - Address Independence Test
Testing HSB 100Mhz clock frequency [hsb_clk_check_tb]
Testing APG counter functions [apg_counter_tests_tb]
    Pattern start is at 3e7
  Testing Counter loading
  Testing Counter address
  Testing Reload loading
  Testing Reload address
  Testing Reload counters from reload registers
  Testing Counter DECR
  Testing Counter INCR
  Testing Counter DECR2
Testing MAR increments, stack nesting [apg_mar_and_stack_tests_tb]
  Testing MAR increments
  Testing Stack nesting, 1st pass
  Testing Stack nesting, 2nd pass
   Stack nesting, 50nS
   Stack nesting, 20nS
Testing APG counter branching [apg_counter_branching_tb]
    Pattern start is at 523
Testing APG timer branching and accuracy [apg_timer_branching_tb]
    Pattern start is at b1
Testing APG interrupt branch logic and addressing [apg_interrupt_branching_tb]
    Pattern start is at 621
Testing APG address generators [apg_address_generators_tb]
    Pattern start is at 532
  Testing uDATA loads
  Testing COMP function
  Testing logic functions
  Testing add
  Testing subtract
  Testing decrement and increment
  Testing Y to X carries and borrows
  Testing X to Y carries and borrows
Testing APG data generator [apg_data_generator_tb]
    Pattern start is at 5d
  Testing uDATA loads
  Testing Count up and down with shift left, 18 bit DMAIN register
  Testing Count up and down with shift left, 18 bit DBASE register
  Testing Shift right, 18 bit DMAIN register
  Testing Shift right, 18 bit DBASE register
  Testing Rotate left, 18 bit DMAIN register
  Testing Rotate right, 18 bit DMAIN register
  Testing Rotate left, 18 bit DBASE register
  Testing Rotate right, 18 bit DBASE register
  Testing Rotate left, 36 bit DMAIN register
  Testing Rotate right, 36 bit DMAIN register
  Testing Rotate left, 36 bit DBASE register
  Testing Rotate right, 36 bit DBASE register
  Testing Shift left, 36 bit DMAIN register
  Testing Shift left, 36 bit DBASE register
  Testing Shift right, 36 bit DMAIN register
  Testing Shift right, 36 bit register
Testing APG error pipelines [apg_error_pipe_tb]
Testing APG data inversions [apg_data_inversions_tb]
    Checking bit1 functions
      Bit1 as Y Address Bits PASSED
      Bit1 as X Address Bits PASSED
    Checking bit2 functions
      Bit2 as Y Address Bits PASSED
      Bit2 as X Address Bits PASSED
    Checking bit1, bit2 logical combinations
      Bit1 AND Bit2 PASSED
      Bit1 OR  Bit2 PASSED
      Bit1 XOR Bit2 PASSED
    Check X and Y parity
        XYodd PASSED
        XYEven PASSED
        Xeven_Yodd PASSED
        Xodd_Yeven PASSED
        Xodd PASSED
        Xeven PASSED
        Yodd PASSED
        Yeven PASSED
    Check DTOPO inversions
      DTopo RAM PASSED
    Check Yindex Counter
      YIndex Counter PASSED
    Check Yindex Mask Inversions
          yindex plus Y, yindex = 0xffff
          yindex plus Y bar, yindex = 0xffff
          yindex plus Y, Y = 0xffff
          yindex plus Y bar, Y = 0x0000
      YIndex Mask Inversions PASSED
    Check XY Equality Functions
          xmain equal to xbase (XEQB)
          xmain less than xbase (XLTB)
          xmain less than or equal to xbase (XLEB)
          xmain equal to xfield or xbase (XEQBORF)
          ymain equal to ybase (YEQB)
          ymain less than ybase (YLTB)
          ymain less than or equal to ybase (YLEB)
          ymain equal to yfield or ybase (YEQBORF)
          xymain equal to xybase (XYEQB)
          xymain less than xybase (XYLTBXF)
          xymain less than xybase (XYLTBYF)
          xymain less than or equal to xybase (XYLEBXF)
          xymain less than or equal to xybase (XYLEBYF)
          inversion from uRAM (INVSNS)
          inversion from uDATA (XORINV)
Testing ECR X Scramble RAM - short march [ecr_xscram_short_march_tb]
Testing ECR Y Scramble RAM - short march [ecr_yscram_short_march_tb]
Testing ECR Row RAM - short march [ecr_rowram_short_march_tb]
Testing ECR Col RAM - short march [ecr_colram_short_march_tb]
Testing ECR dimm bit independence [ecr_dimm_bit_independence_tb]
Testing ECR 5N March [ecr_dimm_hw_long_march_tb]
Testing DBM DRAM - short march [dbm_dimm_short_march_tb]
Testing DBM DIMM 5N March [dbm_dimm_hw_5N_march_tb]
Testing TG Pin Scramble RAM - short march [tg_psram_short_march_tb]
Testing TG timing RAM - short march [tg_timing_ram_short_march_tb]
Testing TG SLVM RAM - short march [tg_slvm_ram_short_march_tb]
Testing TG broadcast mode [tg_broadcast_tb]
Testing TG to PE communications [tg_pe_communication_tb]
Testing PE error generation [pe_error_gen_tb]
Testing PE force drive state [pe_force_drive_state_tb]
Testing PE force drive state [pe_vz_state_tb]
Testing Pin Scramble Format RAM - short march [format_ram_short_march_tb]
Testing Pin Scramble RAM - short march [pe_psram_short_march_tb]
Testing DP ADC [adc_tb]
Testing DP PMU voltage force [pmu_vf_tb]
 Testing DP 1 PMU voltage force DACs
 Testing DP 1 PMU voltage force level accuracy
 Testing DP 2 PMU voltage force DACs
 Testing DP 2 PMU voltage force level accuracy
 Testing DP 3 PMU voltage force DACs
 Testing DP 3 PMU voltage force level accuracy
 Testing DP 4 PMU voltage force DACs
 Testing DP 4 PMU voltage force level accuracy
Testing DP PMU current force [pmu_if_tb]
 Testing DP 1 PMU current force DACs
 Testing DP 1 PMU current force level accuracy
 Testing DP 2 PMU current force DACs
 Testing DP 2 PMU current force level accuracy
 Testing DP 3 PMU current force DACs
 Testing DP 3 PMU current force level accuracy
 Testing DP 4 PMU current force DACs
 Testing DP 4 PMU current force level accuracy
Testing DPS voltage force [dps_vf_tb]
 Testing DP 1 DPSn DACs
 Testing DP 1 DPSn level accuracy
 Testing DP 1 DPSn apg level DAC select path
 Testing DP 1 DPSa DACs
 Testing DP 1 DPSa level accuracy
 Testing DP 2 DPSn DACs
 Testing DP 2 DPSn level accuracy
 Testing DP 2 DPSn apg level DAC select path
 Testing DP 2 DPSa DACs
 Testing DP 2 DPSa level accuracy
 Testing DP 3 DPSn DACs
 Testing DP 3 DPSn level accuracy
 Testing DP 3 DPSn apg level DAC select path
 Testing DP 3 DPSa DACs
 Testing DP 3 DPSa level accuracy
 Testing DP 4 DPSn DACs
 Testing DP 4 DPSn level accuracy
 Testing DP 4 DPSn apg level DAC select path
 Testing DP 4 DPSa DACs
 Testing DP 4 DPSa level accuracy
Testing DP PMU/DPS current measure [range_resistor_tb]
Testing DP PMU comparators [pmu_comp_tb]
 Testing DP 1 PMU comparator DACs
 Testing DP 1 PMU comparator accuracy
 Testing DP 2 PMU comparator DACs
 Testing DP 2 PMU comparator accuracy
 Testing DP 3 PMU comparator DACs
 Testing DP 3 PMU comparator accuracy
 Testing DP 4 PMU comparator DACs
 Testing DP 4 PMU comparator accuracy
Testing PE32 PMU leakage current [pmu_leakage_tb]
Testing PE32 VIH pin level [vih_tb]
 Testing VIH DACs
 Testing VIH level accuracy
 Testing VIH apg level DAC select path
 Testing VIH offset level accuracy
Testing PE32 VIL pin level [vil_tb]
 Testing VIL DACs
 Testing VIL level accuracy
 Testing VIL apg level DAC select path
 Testing VIL offset level accuracy
Testing PE32 VIHH pin level [vihh_tb]
 Testing VIHH DACs
 Testing VIHH level accuracy
 Testing VIHH apg level DAC select path
Testing PE32 VTT pin level [vtt_tb]
 Testing VTT DACs
 Testing VTT level accuracy
Testing PE32 VOH pin level [voh_tb]
 Testing VOH DACs
 Testing VOH level accuracy
Testing PE32 VOL pin level [vol_tb]
 Testing VOL DACs
 Testing VOL level accuracy
Testing PE32 VZ pin level [vz_tb]
 Testing VZ level accuracy
Testing PE32 PE output impedance [pe_rout_tb]
Testing DP PMU voltage clamps [pmu_vclamp_tb]
Testing DP PMU current limit [pmu_ilimit_tb]
Testing DPS switches [dps_switch_tb]
Testing DPS current share [dps_share_tb]
Testing DPS sense resistor bypass diodes [dps_diode_tb]
Testing DPS compensation capacitors [dps_cap_tb]
Testing DP DPS leakage current [dps_leakage_tb]
Testing DP PMU compensation capacitors [pmu_cap_tb]
active dut = 0
Testing DP DPS current capability [dps_imin_tb]
Testing DP HV voltage force [hv_vf_tb]
 Testing HV DACs
 Testing HV level accuracy
Testing DP HV leakage current [hv_leakage_tb]
Testing DP HV current measure [hv_imeas_tb]
Testing PE Verniers [vern_check_tb]
Testing strobe modes [pe_strobe_mode_tb]
Testing PE32 XYAddr Pin Scramble [pe_ps_xy_tb]
  Testing X Address bits
    X Address 50.0MHz Test (20 ns)
  Testing Y Address bits
    Y Address 50.0MHz Test (20 ns)
Testing PE32 Data Pin Scramble [pe_ps_data_tb]
  Testing Data bits
    Data Bits 50.0MHz Test (20 ns)
  Testing Data Strobes
    Data Strobes 20.0MHz Test (50 ns)
Testing PE32 Chip Select Pin Scramble [pe_ps_cs_tb]
  Testing Chip Selects
    Chip Selects 50.0MHz Test (20 ns)
  Testing Chip Select Strobes
    Chip Select Strobes 20.0MHz Test (50 ns)
Testing PE32 Force Pin Scramble [pe_ps_force_tb]
  Testing Drive L/H/Z
    Drive Low  50.0MHz Test (20 ns)
    Drive High 50.0MHz Test (20 ns)
    Tri-State  50.0MHz Test (20 ns)
  Testing Strobe L/H/V/M
    Strobe Low   20.0MHz Test (50 ns)
    Strobe High  20.0MHz Test (50 ns)
    Strobe Valid 20.0MHz Test (50 ns)
    Strobe Mid   20.0MHz Test (50 ns)
Testing PE32 Pin Scramble [pe_ps_lvm_tb]
  Testing Drive 0/1/X
    Drive 0 50.0MHz Test (20 ns)
    Drive 1 50.0MHz Test (20 ns)
    Drive X 50.0MHz Test (20 ns) (HiZ)
  Testing Strobe L/H/V/Z
    Strobe L 20.0MHz Test (50 ns)
    Strobe H 20.0MHz Test (50 ns)
    Strobe V 20.0MHz Test (50 ns)
    Strobe Z 20.0MHz Test (50 ns)
Testing PE32 XYAddr Pin Scramble [pe_ps_xy_ddr_tb]
  Testing X Address bits
    X Address 50.0MHz Test (20 ns)
  Testing Y Address bits
    Y Address 50.0MHz Test (20 ns)
Testing PE32 Data Pin Scramble [pe_ps_data_ddr_tb]
  Testing Data bits
    Data Bits 50.0MHz Test (20 ns)
  Testing Data Strobes
    Data Strobes 20.0MHz Test (50 ns)
Testing PE32 Chip Select Pin Scramble [pe_ps_cs_ddr_tb]
  Testing Chip Selects
    Chip Selects 50.0MHz Test (20 ns)
  Testing Chip Select Strobes
    Chip Select Strobes 20.0MHz Test (50 ns)
Testing PE32 Force Pin Scramble [pe_ps_force_ddr_tb]
  Testing Drive L/H/Z
    Drive Low  50.0MHz Test (20 ns)
    Drive High 50.0MHz Test (20 ns)
    Tri-State  50.0MHz Test (20 ns)
  Testing Strobe L/H/V/M
    Strobe Low   20.0MHz Test (50 ns)
    Strobe High  20.0MHz Test (50 ns)
    Strobe Valid 20.0MHz Test (50 ns)
    Strobe Mid   20.0MHz Test (50 ns)
Testing PE32 Pin Scramble [pe_ps_lvm_ddr_tb]
  Testing Drive 0/1/X
    Drive 0 50.0MHz Test (20 ns)
    Drive 1 50.0MHz Test (20 ns)
    Drive X 50.0MHz Test (20 ns) (HiZ)
  Testing Strobe L/H/V/Z
    Strobe L 20.0MHz Test (50 ns)
    Strobe H 20.0MHz Test (50 ns)
    Strobe V 20.0MHz Test (50 ns)
    Strobe Z 20.0MHz Test (50 ns)
Testing PE32 Timing Generators [pe_tg_format_tb]
  Testing NRZ Format 5.0MHz Test (200 ns) with Edge Strobes
  Testing NRZ Format 5.0MHz Test (200 ns) with Window Strobes
  Testing RTO Format 5.0MHz Test (200 ns) with Edge Strobes
  Testing RTO Format 5.0MHz Test (200 ns) with Window Strobes
  Testing RTZ Format 5.0MHz Test (200 ns) with Edge Strobes
  Testing RTZ Format 5.0MHz Test (200 ns) with Window Strobes
Testing PE32 Timing Generators [pe_tg_dclk_format_tb]
  Testing DCLKPOS Format 5.0MHz Test (200 ns) with Edge Strobes
  Testing DCLKPOS Format 5.0MHz Test (200 ns) with Window Strobes
  Testing DCLKNEG Format 5.0MHz Test (200 ns) with Edge Strobes
  Testing DCLKNEG Format 5.0MHz Test (200 ns) with Window Strobes
Testing PE32 Timing Generators [pe_tg_mux_mode_tb]
  Testing MUX Mode 5.0MHz Test (200 ns) with Edge Strobes
  Testing MUX Mode 5.0MHz Test (200 ns) with Window Strobes
Testing VMC FIFO Resident Loop counter branching [vmc_fifo_loop_branching_tb]
    Builtin Pure Logic Pattern start is at 0
    Running vmc_fifo_loop1_np_pat
    PASS: vmc_fifo_loop1_np_pat
    Running vmc_fifo_loop2_np_pat
    PASS: vmc_fifo_loop2_np_pat
    Running vmc_fifo_loop3_np_pat
    PASS: vmc_fifo_loop3_np_pat
    Running vmc_fifo_loop4_np_pat
    PASS: vmc_fifo_loop4_np_pat
    Running vmc_fifo_loop5_np_pat
    PASS: vmc_fifo_loop5_np_pat
    Running vmc_fifo_loop6_np_pat
    PASS: vmc_fifo_loop6_np_pat
Testing VMC RAM Resident Loop counter branching [vmc_ram_loop_branching_tb]
    Builtin Pure Logic Pattern start is at 0
    Running vmc_ram_loop_np_pat
    PASS: vmc_ram_loop_np_pat
Testing LVM Subroutine Branching [lvm_subroutines_tb]
Testing LVM Subroutine Branching DDR [lvm_subroutines_ddr_tb]
Testing Scan Functionality [scan_tb]
  Standard Mode SCAN Tests
  Split Mode SCAN Tests
  TG Hold SCAN Tests
Testing Scan DDR Functionality [scan_ddr_tb]
  Standard Mode SCAN Tests
  Split Mode SCAN Tests
  TG Hold SCAN Tests
Testing HSB sec. connections [apg_sec_tb].
active dut = 0
active dut = 1
Testing ECR [ecr1_tb]
Testing first 36 ECR data inputs with 18X, 0Y
 Testing ECR0 first 36 error lines
 Testing ECR1 first 36 error lines
Testing ECR [ecr2_tb]
Testing last 36 ECR data inputs with 18X, 0Y
 Testing ECR0 last 36 error lines
 Testing ECR1 last 36 error lines
Testing ECR [ecr3_tb]
Testing ECR address inputs with 18X, 3Y and full speed configuration
 Testing ECR0 addressing
  ECR0 first row
  ECR0 second row
  ECR0 third row
  ECR0 last row
  ECR0 diagonal
 Testing ECR1 addressing
  ECR1 first row
  ECR1 second row
  ECR1 third row
  ECR1 last row
  ECR1 diagonal
Testing ECR [ecr4_tb]
Testing ECR address inputs with 5X, 16Y and full speed configuration
 Testing ECR0 addressing
  ECR0 first column
  ECR0 second column
  ECR0 third column
  ECR0 last column
  ECR0 diagonal
 Testing ECR1 addressing
  ECR1 first column
  ECR1 second column
  ECR1 third column
  ECR1 last column
  ECR1 diagonal
Testing ECR [ecr5_tb]
Testing ECR clear with full speed configuration, 18X, 3Y
 Testing ECR0 clear
 Testing ECR1 clear
Testing ECR [dbm1_tb]
Testing DBM read widths with minimum speed configuration, 18X, 6Y
Testing ECR [dbm2_tb]
Testing DBM read speeds with 36 bit configuration, 18X, 3Y
Testing ECR [dbm3_tb]
Testing DBM write widths with minimum speed configuration, 18X, 6Y
Testing ECR [dbm4_tb]
Testing DBM write speeds with 36 bit configuration, 18X, 3Y
Testing ECR [dbm5_tb]
Testing DBM write to ECR capture with full speed configuration, 18X, 3Y
 Testing DBM capture to ECR0
  DBM to ECR0 first row
  DBM to ECR0 second row
  DBM to ECR0 third row
  DBM to ECR0 last row
  DBM to ECR0 diagonal
Testing ECR [ dbm6_tb ]
Testing DBM read widths with sequential configuration, 18X, 6Y
Testing CPUI in multiple sites per controller [multisite_cpui_tb]
multisite_cpui_tb PASSED.
Testing APG in multiple sites per controller [multisite_apg_tb]
multisite_apg_tb PASSED.
PE_Temperature_Display [pe_temperature_display_tb]
09:50:27   Cyc= 0.00ns   Vih=4.00v/4.00v/4.00v/4.00v   Vil=0.00v/0.00v/0.00v/0.00v
 HSB2              temp[low/hi]            temp[low/hi]
  HSB LVM  local = 29 [  0/ 70]   remote = 32 [  0/ 70]
  HSB ECR  local = 31 [  0/ 70]   remote = 35 [  0/ 70]
 Temperatures on PEmodule1
  U14= 35.0   U22= 38.5   U18= 42.1    U4= 43.0
  U17= 33.8    U3= 41.1   U20= 41.5    U6= 41.7
  U16= 33.6    U2= 37.4   U21= 41.7    U7= 45.4
  U19= 36.4    U5= 41.3   U15= 42.8    U1= 48.7
  PE 1 thermal sensor = 43 (low limit = 81, high limit = 86)
 Temperatures on PEmodule2
  U14= 36.4   U22= 40.9   U18= 44.8    U4= 46.4
  U17= 37.0    U3= 39.5   U20= 45.6    U6= 49.1
  U16= 38.5    U2= 39.7   U21= 44.2    U7= 48.9
  U19= 37.2    U5= 39.3   U15= 43.0    U1= 47.5
  PE 2 thermal sensor = 46 (low limit = 81, high limit = 86)
 Temperatures on PEmodule3
  U14=-231.0   U22= 44.4   U18=-222.4    U4= 47.3
  U17=-220.0    U3= 41.7   U20=-219.6    U6= 49.9
  U16=-220.6    U2= 44.8   U21=-219.2    U7= 48.9
  U19=-221.2    U5= 41.1   U15=-219.0    U1= 50.7
  PE 3 thermal sensor = 45 (low limit = 81, high limit = 86)
 Temperatures on PEmodule4
  U14= 36.8   U22= 38.7   U18= 39.9    U4= 43.0
  U17= 39.1    U3= 40.3   U20= 41.1    U6= 43.8
  U16= 38.7    U2= 42.6   U21= 41.3    U7= 45.0
  U19= 36.6    U5= 39.9   U15= 43.0    U1= 44.8
  PE 4 thermal sensor = 41 (low limit = 81, high limit = 86)
SystemDiag summary [diag_summary_tb]
    Pass number : 1
    Time for this pass : 00:06:59
    Total time : 00:07:08
Final Bin: pass_bin
Done: 04/29/20 09:50:29
TestDone...bin = pass_bin,pass_bin

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Established in 1998, SDI has now built up an international network of sales agents and offices.

SDI has evolved into one of the largest semiconductor equipment brokerages by concentrating on professionalism, customer service and value for money.

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Due to heavy demand from our many customers,
SDI-Fabsurplus has decided to better serve an elite selection of our regular customers by offering a Subscription Fee service,
providing a premium level of service in which our customers can opt-in to gain immediate access
and regular weekly updates to the most valuable information about semiconductor equipment available in the worldwide market,
together with prioritised support directly from our sales team via phone, website and e-mail.



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Ask SDI fabsurplus.com! If you can't find what you need, or are looking for a specific piece of semiconductor equipment. Let us know what type of semiconductor manufacturing equipment you would like to buy, and we will conduct a search for what you are looking for.

Inquiry



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SDI-Fabsurplus Srl Italy, and SDI-FABSURPLUS LLC. N. America




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