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NEXTEST MAVERICK PT II Automated Test Equipment for Sale


SDI fabsurplus.com is pleased to announce the availability of the following listed used NEXTEST MAVERICK PT II Automated Test Equipment.
Please click on the "Send More Details" button at the end of the MAVERICK PT II description, if you'd like to get more details, photos and specifications of this Automated Test Equipment, and your request for this equipment will be forwarded to our SDI sales representatives automatically.
This NEXTEST MAVERICK PT II Automated Test Equipment is available for immediate sale.
Crating, refurbishment and delivery for this equipment can be quoted on request.


NEXTEST MAVERICK PT II Equipment Details

SDI ID: 99382
Manufacturer: NEXTEST
Model: MAVERICK PT II
Description: Automated Test Equipment
Version: TEST
Vintage: Inquire
Quantity: 1
Sales Condition: as is where is
Lead Time: immediately
Sales Price: Inquire
Comments:

-in working condition

-see attached photo for details

-diagnostic report:

The test program is loaded

TestStarted(1)...

Started: 05/18/20 09:30:58
                                       Site 1
  Board      Serial    PWB    PWB   PWA    PWA   LVM    DBM    Scan   ECR    X     Y     D
  Name       Number   Number  Rev  Number  Rev  Kbits  Mbits  Mbits  Mbits  bits  bits  bits
  ---------------------------------------------------------------------------------------------
   PTI       x   500000    3  500001    7                                                
   PE1       x   501683    4  501873   10   2048                                         
   PE2       x   501683    4  501873   10   2048                                         
   APG       x   501682    3  501872   32   2048     36      8                           
   ECR       x   500732    9  501255   16                         36    10    10    36  
 
Nextest software release:  C:\nextest\v2.13.16-LITE\Bin\Ui.exe
Testing APG read,write registers via cpu [apg_rw_regs_tb]
       Address registers and LBDATA
       MAR and INTA
       JAM, DATA, INDEX, VAR and SCAN PTR
       Unique values
Testing APG counter RAM - short march [apg_counter_ram_short_march_tb]
Testing APG reload RAM - short march [apg_reload_ram_short_march_tb]
Testing APG DTOPO RAM - short march [apg_dtopo_ram_short_march_tb]
Testing APG uRAM - short march [apg_uram_ram_short_march_tb]
Testing APG Cycle Length RAM - short march [apg_cycle_ram_short_march_tb]
Testing APG DAC RAM - short march [apg_dac_ram_short_march_tb]
Testing APG ATOPO RAM - short march [apg_atopo_ram_short_march_tb]
Testing APG SCAN RAM - short march [apg_scan_ram_short_march_tb]
    SCAN RAM depth is 0x100000
Testing APG Buffer Memory - short march [apg_buf_ram_short_march_tb]
    Buffer Memory depth is 0x100000 - 0x400 X, 0x400 Y
Testing APG VAR Counter RAM [apg_vector_ram_march_tb]
Testing APG vRAM - short march [apg_vram_ram_short_march_tb]
    LVM Memory depth is 0x200000
Testing APG counter functions [apg_counter_tests_tb]
    Pattern start is at c5
    Counter loading
    Counter address
    Reload loading
    Reload address
    Reload counters from reload registers
    Counter DECR
    Counter INCR
    Counter DECR2
Testing APG MAR increments, stack nesting [apg_mar_and_stack_tests_tb]
   MAR increments
   Stack nesting, 1st pass
   Stack nesting, 2nd pass
   Stack nesting, 50nS
   Stack nesting, 30nS
Testing APG counter branching [apg_counter_branching_tb]
    Pattern start is at 1fe
Testing APG timer branching and accuracy [apg_timer_branching_tb]
    Pattern start is at 34e
Testing APG interrupt branch logic and addressing [apg_interrupt_branching_tb]
    Pattern start is at 2f4
Testing APG address generators [apg_address_generators_tb]
    Pattern start is at 20a
    Checking uDATA loads
    Checking COMP function
    Checking logic functions
    Checking add
    Checking subtract
    Checking decrement and increment
    Checking Y to X carries and borrows
    Checking X to Y carries and borrows
Testing APG data generator [apg_data_generator_tb]
    Pattern start is at 328
    Checking uDATA loads
    Count up and down with shift left, 18 bit register
    Shift right, 18 bit register
    Rotate left, 18 bit register
    Rotate right, 18 bit register
    Rotate left, 36 bit register
    Rotate right, 36 bit register
    Shift left, 36 bit register
    Shift right, 36 bit register
Testing APG error pipelines [apg_error_pipe_tb]
Testing APG data paths [apg_data_paths_tb]
    Buffer Memory depth is 0x100000 - 0x400 X, 0x400 Y
    Pattern start is at 49f
    Checking JAM and Data Register Paths
    Checking Buffer Memory Path
    Checking Buffer Memory Writes
    Checking Buffer Memory x18 Path
    Checking Buffer Memory x18 Writes
       30nS writes
Testing APG data inversions [apg_data_inversions_tb]
    Pattern start is at 374
    Checking bit2 functions
    Checking bit1 functions
    Check bit1, bit2 logical combinations
        AND
        OR
        XOR
    Check X and Y parity
        xyodd
        xyeven
        xeven_yodd
        xodd_yeven
        xodd
        xeven
        yodd
        yeven
    Check DTOPO inversions
        X or Y
        X and Y
        X xor Y
    Check Yindex counter
    Check Yindex inversions
          Yindex masks
          yindex plus Y, yindex = 0xffff
          yindex plus Y bar, yindex = 0xffff
          yindex plus Y, Y = 0xffff
          yindex plus Y bar, Y = 0x0000
    Pattern start is at 3f5
          xmain equal to xbase (XEQB)
          xmain less than xbase (XLTB)
          xmain less than or equal to xbase (XLEB)
          xmain equal to xfield or xbase (XEQBORF)
          ymain equal to ybase (YEQB)
          ymain less than ybase (YLTB)
          ymain less than or equal to ybase (YLEB)
          ymain equal to yfield or ybase (YEQBORF)
          xymain equal to xybase (XYEQB)
          xymain less than xybase (XYLTBXF)
          xymain less than xybase (XYLTBYF)
          xymain less than or equal to xybase (XYLEBXF)
          xymain less than or equal to xybase (XYLEBYF)
          inversion from uRAM (INVSNS)
          inversion from uDATA (XORINV)
Testing APG scan pointer [apg_scan_address_tb]
    Pattern start is at 48f
Testing APG vector address (VAR) [apg_vector_address_tb]
    Pattern start is at 494
Testing APG VAR counter functions [apg_var_counter_tests_tb]
    Counter loading
    Counter address
    VAR Counter DECR
Testing APG VAR increments, stack nesting [apg_var_and_stack_tests_tb]
   VAR increments
   Stack nesting, 1st pass
   Stack nesting, 2nd pass
   Stack nesting, 50nS
   Stack nesting, 30nS
Testing APG VAR counter branching [apg_var_counter_branching_tb]
    var/mar counter branching
Testing APG RAM read only paths [apg_ram_current_outputs_tb]
Testing PE TG count RAM [pe_tg_count_march_tb]
 Testing PE1
 Testing PE2
Testing PE TG format RAM [pe_tg_format_march_tb]
 Testing PE1
 Testing PE2
Testing PE VIHH RAM [pe_vihh_march_tb]
 Testing PE1
 Testing PE2
Testing PE Pin Scramble RAM [pe_psram_march_tb]
 Testing PE1
 Testing PE2
Testing PE LVM RAM [pe_lvm_march_tb]
 Testing PE1
 Testing PE2
Testing PE Broadcast mode [pe_broadcast_tb]
 Testing PE1
 Testing PE2
Testing PE16 ADC [adc_tb]
Testing PE16 PMU current force [pmu_if_tb]
 Testing PE16 1 PMU current force DACs
 Testing PE16 1 PMU current force level accuracy
 Testing PE16 1 PMU current force apg level DAC select path
 Testing PE16 2 PMU current force DACs
 Testing PE16 2 PMU current force level accuracy
Testing PE16 PMU voltage force [pmu_vf_tb]
 Testing PE16 1 PMU voltage force DACs
 Testing PE16 1 PMU voltage force level accuracy
 Testing PE16 1 PMU voltage force apg level DAC select path
 Testing PE16 2 PMU voltage force DACs
 Testing PE16 2 PMU voltage force level accuracy
Testing PE16 DPS voltage force [dps_vf_tb]
 Testing PE16 1 DPSn DACs
 Testing PE16 1 DPSn level accuracy
 Testing PE16 1 DPSn apg level DAC select path
 Testing PE16 1 DPSa DACs
 Testing PE16 1 DPSa level accuracy
 Testing PE16 1 DPSa apg level DAC select path
 Testing PE16 2 DPSn DACs
 Testing PE16 2 DPSn level accuracy
 Testing PE16 2 DPSa DACs
 Testing PE16 2 DPSa level accuracy
Testing PE16 PMU/DPS current measure [range_resistor_tb]
Testing PE16 PMU_F FETs, VBK FETs, K1 and K2 Relays [relays_tb]
 Testing PMU_F FETs
 Testing VBK FETs
 Testing K1 Relays
 Testing K2 Relays
Testing PE16 PMU comparators [pmu_comp_tb]
 Testing PE16 1 PMU comparator DACs
 Testing PE16 1 PMU comparator accuracy
 Testing PE16 1 PMU comparator apg level DAC select path
 Testing PE16 2 PMU comparator DACs
 Testing PE16 2 PMU comparator accuracy
Testing PE16 PMU leakage current [pmu_leakage_tb]
Testing PE16 background voltage [vbk_tb]
 Testing background voltage DACs
 Testing background voltage level accuracy
 Testing background voltage apg level DAC and PE select paths
 Testing background voltage apg level bit weight paths
Testing PE16 VIHH pin level [vihh_tb]
 Testing VIHH DACs
 Testing VIHH level accuracy
 Testing VIHH apg level DAC select path
Testing PE16 VIH pin level [vih_tb]
 Testing VIH DACs
 Testing VIH level accuracy
 Testing VIH apg level DAC select path
 Testing VIH offset level accuracy
Testing PE16 VIL pin level [vil_tb]
 Testing VIL DACs
 Testing VIL level accuracy
 Testing VIL apg level DAC select path
 Testing VIL offset level accuracy
Testing PE16 IOH pin level [ioh_tb]
 Testing IOH level accuracy
Testing PE16 IOL pin level [iol_tb]
 Testing IOL level accuracy
Testing PE16 VZ pin level [vz_tb]
 Testing VZ level accuracy
Testing PE16 VOH pin level [voh_tb]
 Testing VOH DACs
 Testing VOH level accuracy
 Testing VOH apg level DAC select path
Testing PE16 VOL pin level [vol_tb]
 Testing VOL DACs
 Testing VOL level accuracy
 Testing VOL apg level DAC select path
Testing PE16 PMU voltage clamps [pmu_vclamp_tb]
Testing PE16 PMU current limit [pmu_ilimit_tb]
Testing PE16 DPS switches [dps_switch_tb]
Testing PE16 DPS current share [dps_share_tb]
Testing PE16 DPS sense resistor bypass diodes [dps_diode_tb]
Testing PE16 DPS compensation capacitors [dps_cap_tb]
Testing PE16 PMU compensation capacitors [pmu_cap_tb]
Testing PE16 DPS current capability [dps_imin_tb]
Testing PE force pins [pe_force_pins_tb]
 Testing PE1
 Testing PE2
Testing PE strobe modes [pe_strobe_mode_tb]
 Testing PE1
 Testing PE2
Testing PE tg formats [pe_tg_format_tb]
 Testing PE1
 Testing PE2
Testing PE tg dclk formats [pe_tg_dclk_format_tb]
 Testing PE1
 Testing PE2
Testing PE tg io formats [pe_tg_io_format_tb]
 Testing PE1
 Testing PE2
Testing PE tg counters [pe_tg_counter_tb]
 Testing PE1
 Testing PE2
Testing PE vihh maps [pe_vihh_map_tb]
 Testing PE1
 Testing PE2
Testing PE pin scramble [pe_ps_ad_tb]
 Testing PE1
 Testing PE2
Testing PE pin scramble [pe_ps_cs_tb]
 Testing PE1 active low
 Testing PE2 active low
 Testing PE1 active high
 Testing PE2 active high
Testing PE pin scramble [pe_ps_lvm_tb]
 Testing PE1
 Testing PE2
Testing PE pin scramble [pe_ps_scan_tb]
 Testing PE1
 Testing PE2
Testing PE mux mode [pe_mux_mode_tb]
 Testing PE1
 Testing PE2
Testing PE first error counter [pe_first_error_tb]
 Counter start test, tgmode 0
  Testing PE1
  Testing PE2
 Counter start test, tgmode 1
  Testing PE1
  Testing PE2
 Counter bit test, tgmode 0
  Testing PE1
  Testing PE2
 Counter bit test, tgmode 1
  Testing PE1
  Testing PE2
Testing PE error [pe_error_flag_tb]
 Testing PE1
 Testing PE2
Testing PE abort [pe_abort_tb]
 Testing PE1
 Testing PE2
Testing PE VAR Path (pe_var_path_tb)
 Testing PE1
 Testing PE2
Testing PE Real Time Error Catch Counter [pe_rtec_counter_tb]
  Testing PE1
  Testing PE2
Testing ECR X Scramble RAM - short march [ecr_xscram_short_march_tb]
    X Scramble depth is 0x8000
Testing ECR Y Scramble RAM - short march [ecr_yscram_short_march_tb]
    Y Scramble depth is 0x8000
Testing ECR Row Capture RAM - short march [ecr_rowram_short_march_tb]
    Row RAM depth is 0x8000
Testing ECR Column Capture RAM - short march [ecr_colram_short_march_tb]
    Column RAM depth is 0x8000
Testing ECR Main Capture RAM - short march [ecr_mainram_short_march_tb]
    Main RAM depth is 0x100000
Testing ECR Scanning of Row Catch RAM [ecr_row_scan_tb]
Testing ECR Scanning of Column Catch RAM [ecr_col_scan_tb]
Testing ECR Scanning of Main Catch RAM [ecr_main_scan_tb]
    Main RAM depth is 0x100000
      Scanning X and Y
      Varying data widths
         x32, 0xa X, 0xa Y
         x16, 0xb X, 0xa Y
         x8, 0xc X, 0xa Y
         x4, 0xd X, 0xa Y
         x2, 0xe X, 0xa Y
         x1, 0xf X, 0xa Y
      Scanning X only
      Scanning Y only
Testing ECR Error Catching [ecr_error_catching_tb]
    Data Crosspoint
       1st pin list, 0x20 pins
       Varying data widths
    Address Crosspoint
Testing ECR Logic Error Catching [ecr_logic_error_catch_tb]
    First Vectors
    Last Vectors
    Before Error
    After Error
    Only Errors
    Center Error
Testing ECR DDR Capture [ecr_ddr_capture_tb]
    DDR Capture
SystemDiag summary [diag_summary_tb]
    Pass number : 1
    Time for this pass : 00:01:31
    Total time : 00:01:33
Final Bin: pass_bin
Done: 05/18/20 09:32:29
TestDone...bin = pass_bin

 

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